1.The segment registers in 8086 are
(a) 3 (b) 2 (c) 4 (d) 1
Ans: c
2.A subroutine is always terminated with a
(a) INT instruction (b) ESC instruction (c) RET instruction (d) RETI instruction
Ans: c
3.The addressing mode of MOV AX, 55H [ BX ] [ SI ] is
(a)Base index addressing (b) Base relative plus index addressing
(c) Relative index addressing (d)Index addressing
Ans: b
4.The BIU fetches ___ number of instruction bytes ahead from the memory to speed up program execution.
(a) Six (b)Seven (c) Four (d) Five
Ans: a
5. The speed of microprocessor depends on
(a) Clock (b) Address bus width (c)Memory
(d)None of the above
Ans: a
6. Maskable interrupts can be recognized by 8086 only if ____ is set.
(a) IF
(b) CF
(c) AC
(d) DF
Ans: a
7. The functional unit(s) in 8086 is (are)
(a) Two
(b) Three
(c) one
(d) Four
Ans: a
8. In 8086,____has the highest priority among all the interrupts
(a) NMI
(b) DIV
(c) Type
(d) Overflow
Ans: a
9.When 8086 performs ______, when read pin is low.
(a)write operation
(b)read operation
(c)memory operation
(d)I/O operation
Ans: b
10. BHE signal of 8086 processor is used to interface the
(a) Even bank memory
(b) Odd bank memory
(c) I/O
(d) DMA
Ans: b
11. Which of the following statements is not true for 8086 microprocessor
(a) Coprocessor is interfaced in MAX mode.
(b) Coprocessor is interfaced in MIN mode.
(c) I/O can be interfaced in MAX/MIN mode.
(d) Supports pipelining.
Ans: b
12. The length of flag register in 8086 is ______but only ________ bits are used.
(a) 16 bits and 9
(b) 8 bits and 9
(c) 16 bits and 8
(d) 16 bits and 10
Ans: a
14. A microprocessor has 20 bit address lines. The size of the memory that can be interfaced with the processor is
(a) 64 KB
(b) 1 MB
(c) 10 MB
(d) 2 MB
Ans: b
15. If SP = 4FFFAH, after execution of POP AX instruction SP is
(a) 4FFFCH
(b) 4FFF8H
(c) 4FFECH
(d) 4FFE8H
Ans: a
16. If direction flag = 0, on executing MOV SB instruction the address of the string is
(a) Decremented
(b) Incremented
(c) Not changed
(d) None of the above
Ans: b
17.The segment used during the execution of interrupt and CALL operation is
(a) Code Segment
(b) Data segment
(c) Extra segment
(d) Stack segment
Ans: d
18.The method of accessing data in stack and queue is
(a) LIFO, LILO
(b) FIFO, LIFO
(c) LIFO, FIFO
(d) LILO, FIFO
Ans: c
19.The LOCK prefix instruction, when executed
(a) Locks the registers
(b) Locks the I/O devices
(c) Locks the bus
(d) Locks the Master
Ans: c
20.A high on HOLD pin indicates
(a) The master processor is holding the bus
(b) Another master is requesting to take over the system bus
(c) The master is holding the slave bus
(d) All the above
Ans: b
21.The following flag is set when the result of a signed operation is too large positive/ negative number
(a) Trap flag
(b) Direction flag
(c) Overflow flag
(d) Auxiliary Carry flag
Ans: c
22.The instruction IN AL, 80H copies
(a) 8 bit content from AL to 80H port address
(b) 8 bit content from 80H port address to AL
(c) 16 bit content from AL to 80H port address
(d) 16 bit content from 80H port address to AL
Ans: b
23.Fetching next instruction while the current instruction is executing is called ________ and this is done to increase the ________ of execution.
(a) Pipelining, speed
(b) Speeding up, throughput
(c) Pipelining, throughput
(d) Queuing, speed
Ans: a
24.The pins QS1, QS0 belongs to ___ mode and reflects the status of _____________.
(a) MIN, interrupt register
(b) MAX, interrupt register
(c) MAX, instruction Queue
(d) MIN, instruction Queue
Ans: c
25. When the status bits (,, ) are 1 1 0, it represents
(a) I/O read
(b) memory read
(c) I/O write
(d) memory write
Ans: d
26. The content of the internal registers CS, IP after Reset is pressed are
(a) 0100H, F000H, FFF0H
(b) 0000H, F000H, FFF0H
(c) 0100H, FF00H, FFF0H
(d) 0100H, FFFFH, FFF0H
Ans: b
27. INT 2 is a _____ interrupt and the address of ISR will be at ____
(a) NMI, 000AH
(b) breakpoint, 0008H
(c) NMI, 0008H
(d) single step interrupt, 0008H
Ans: c
28.The instruction used to mask the upper 8 bits of BX register is
(a) OR BX, 00FFH
(b) AND BX, 00FFH
(c) ANL BX, 00FFH
(d) ORL BX, 00FFH
Ans: b
29.The addressing mode of CLC instruction is
(a) Immediate
(b) Direct
(c) Implied
(d) Indirect
Ans: c
30.The correct option for SUB and CMP instruction is
(a) Both the instructions perform subtraction operation and store the result, sub affects the flag.
(b) Both the instructions perform subtraction operation, comparison stores the result and sub affects the flag.
(c) Both the instructions perform comparison operation, sub stores the result and comparison affects the flag.
(d) Both the instructions perform subtraction operation and they affect the flags, sub stores the result.
Ans: d
31.The buses multiplexed in 8086 are
(a) Higher order address bus and data bus
(b) Lower order address bus and data bus
(c) Higher order address bus and lower order data bus
(d) Lower order address bus and higher order data bus
Ans: b
